4+ years- Verification Engineers(System Verilog + OVM/UVM) & RTL Design/ FPGA Engineers (RTL coding, Micro architecture/ STA synthesis) for Bangalore location.
If interested please share your resume at c_utkarshas@smartplayin.com
Follow @jobinindia
If interested please share your resume at c_utkarshas@smartplayin.com
Follow @jobinindia
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