Verification Engineers(System Verilog + OVM/UVM), #Bangalore

4+ years Verification Engineers(System Verilog + OVM/UVM) @ SmartPlay Technologies for Bangalore location.

If interested please share your resume at c_antrag@smartplayin.com

Experienced verification engineers, 8-15 yrs,, Intel

Experienced verification engineers to work on cutting edge Mixed signal SOCs for wearable and IoT group of Intel. 8-15 years of relevant experience, 

Should have experience in verification strategy of full chip; worked on embedded processor based SOCs, familiar with CPU subsystem, memory controllers, various peripheral device protocols. 

Contact mohan.narasimhan[at]intel.com

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4+ yrs, Verification Engineers, Bangalore

4+ years- Verification Engineers(System Verilog + OVM/UVM) & RTL Design/ FPGA Engineers (RTL coding, Micro architecture/ STA synthesis) for Bangalore location. 

If interested please share your resume at c_utkarshas@smartplayin.com

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Verification Engineers in Bangalore

Verification Engineers in Bangalore...

Design Verification Engineers

Experience:  3-15 Years. Location: Bangalore, Pune

Job Description
• Create verification plans for SoC / IP level verification.
• Create test benches in System Verilog / Specman.
• Write test cases in C / C++, Assembly, e / SV etc.
• Utilize advanced verification methodologies like VMM / OVM / UVM / eRM for writing verification environments.
• Expertise in standard IP blocks and protocols such as PCIe, USB 3.0, SATA, Ethernet, TCP/IP, IPSec, iSCSI, DDR3.
• Extensively worked on debugging tests in RTL / GLS both at SOC and IP level.
• Worked on generating code / functional coverage and analyzing the results.
• Low power verification techniques using industry standard tools.
• Worked on writing assertions using standard languages.
• Write tools and scripts in Perl and other scripting languages to enhance the verification process.
• Excellent problem solving and debugging skills.

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