Showing posts with label Verification Engineer jobs. Show all posts
Showing posts with label Verification Engineer jobs. Show all posts

Monday, July 4, 2016

Verification Engineers, 4-6 yrs, #Hyderabad

Verification Engineers : 

Skills : Knowledge of systemverilog & VMM/UVM methodology. 

Preferred experience with any of the protocols PCIe/USB/SATA Understanding of serdes or mixed signal design/verification flow is preferred. 

Experience : 4-6 Years | 

Location : Hyderabad 

Interested share resume to gunjan@incise.in

Wednesday, August 5, 2015

4+ yrs, Verification Engineers, Bangalore

4+ years- Verification Engineers(System Verilog + OVM/UVM) & RTL Design/ FPGA Engineers (RTL coding, Micro architecture/ STA synthesis) for Bangalore location. 

If interested please share your resume at c_utkarshas@smartplayin.com




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