Verification Engineers :
Skills : Knowledge of systemverilog & VMM/UVM methodology.
Preferred experience with any of the protocols PCIe/USB/SATA Understanding of serdes or mixed signal design/verification flow is preferred.
Experience : 4-6 Years |
Location : Hyderabad
Interested share resume to gunjan@incise.in
Skills : Knowledge of systemverilog & VMM/UVM methodology.
Preferred experience with any of the protocols PCIe/USB/SATA Understanding of serdes or mixed signal design/verification flow is preferred.
Experience : 4-6 Years |
Location : Hyderabad
Interested share resume to gunjan@incise.in
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