@INTEL #Bangalore #Job Openings

INTEL Bangalore Openings 
Reach Srinivas with updated resume to Srinivasx.k.r@intel.com

1)Soc Verification-OVM/UVM,Verilog,IP Verification/PCIE/Subsytem level/DDR memory side 3-17 Yrs 

2)Linux Kernel +WLAN Driver Developer 4-10 Yrs 

3)WLAN/Wifi Driver Developer 4-10 Yrs

4)Graphics Virtualization and Debug Engineer 3-12 Yrs

5)BT/WLAN COEX Testing 2-12 Yrs

6)Network Software Engineer-C,DPDK,Networking Protocols Development 3-15 yrs

7)PCB Design (IC Package Design)-3-15 Yrs

8)WLAN/Wifi Testing/Testers 3-15 Yrs

9)Lab Manager -5-20Yrs

Note: Please do not apply applicable for following

1)Freshers- Apply on Career Site only do not forward me any resumes
2) Vendors/Consultancy

IP Verification,SoC Verification, DFT and Physical Design. 4+ yrs, #Singapore

Graphene hiring IP Verification,SoC Verification, DFT and Physical Design professionals with 4+ yrs experience for Singapore location

veena.jadav@graphsemi.com














Top #Adsense keywords: Insurance,   Loans,  Mortgage,   Attorney,  Credit,  Lawyer,  Donate,  Degree,  Hosting,  Claim  

Deep Learning Experts, nVidia, US

Deep Learning Experts! 

NVIDIA is widely considered to be one of the technology world’s most desirable employers doing things in Deep Learning that no other computer company can, from creating DGX-1, the world’s first deep learning supercomputer to accelerating every major Deep Learning framework with cuDNN. 

Needs people like to join on this exciting journey! 

If you are open to passively and confidentially exploring a role within the organization. 

Check out https://lnkd.in/eiXNi_7

rkhanna@nvidia.com

Synapse is hiring Physical Design Engineers in Bangalore

We are aggressively Hiring for Physical Design Engineers in Bangalore...

Physical Design Engineers

Experience:  4-8 Years. Location: Bangalore

Job Description: 

• Responsible for full chip implementation of complex SoCs (RTL-to-GDSII)
• Work on Place and Route in 45nm and 28nm technologies  
• Define the floor plan, including pin placement, power busing, placement of blocks and macros
• Physical Synthesis and Timing Closure for MMMC
• Design complex clocking structures for MMMC, Noise Analysis, X-talk Optimization and DFM Routing
• Physical Verification including DRC, ERC and LVS. Static and Dynamic IR Analysis
• Perl/tcl scripting proficiency Timing Analysis using STA. 

Desired Skills and Experience

Desired Skills: 

• Experience using Synopsys ICC, Magma Talus, Cadence Encounter, Mentor Olympus or Atoptech tools
• Successful tape out experience of multiple complex chips (10M+ gates) at 45 or 28 nm  
• Expertise in floor planning, Physical Synthesis, CTS, Routing
• Knowledge of low power flow (power gating, multi-Vt, voltage islands, dynamic voltage scaling, body biasing, etc.)
• Hands on experience with STA (Primetime), Power analysis (Apache), DRC / LVS (Calibre), Noise analysis (Celtic / PT-SI)
• Deep sub-micron design problems and solutions (leakage power, signal integrity, DFM etc.)
• Circuit level comprehension of time critical paths in the design
• Programming experience in tcl, Perl.

Please forward your updated resume ASAP, and also please refer your friends & colleagues as well:

Many thanks,

Jayaprakash Yangal 

Synapse Techno Design Innovations Pvt Ltd | Prestige Shantiniketan Commercial Complex, 8th Floor, Tower C, Gate No 2, ITPL Road, Whitefield Bangalore – 560066 | Karnataka, INDIA|

Phone Number: +91 80-67539100| Email: jayaprakash@synapse-da.com | www.synapse-da.com