The details of few of the openings are:
Freescale
Position : WIRELESS-Verification Engineers/Leads
Location Noida
Date Posted
Responsibilities
Responsible for functional verification and silicon validation of Cellular, Application Processors and Networking SoC's using advanced directed, random and formal verification techniques . May be required to design, enhance or maintain full fledged SoC testbench/ testbench components. Would be required to write testcases in C & Assembly, and should be capable of understanding/enhancing RTL code related to complex design blocks such as caches, memory sub-systems, microprocessor cores and application specific IP.
Must be skilled in RTL Design and functional verification of large SoC's / FPGAs employing a combination of directed and formal techniques. Hands-on experience with different aspects of verification like logic equivalence, property checking, functional & code coverage metrics, assertions, timing verification desired. Should be skilled in Verilog/VHDL coding, experienced with tools such as VCS/NC-Verilog/Modelsim. Prior work experience with verification of embedded processor cores shall be a plus . Knowledge of PERL/TCL and scripting is a must . Higher level language experience with System C , System Verilog shall be a plus . Familiarity with silicon validation desired.
Requirements
Candidate must possess at least a Bachelor of Engineering/Technology or Master of Engineering/Technology in Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent.
Required skill(s): RTL Design.
At least 3 year(s) of working experience in the related field is required for this position.
Position : WIRELESS-Digital Design Engineers /Leads
Location Noida
Date Posted
Responsibilities
Digital IP/ Subsystem Design for future Mobile and Networking products. Responsible for working with global teams in understanding requirements and implementing into design.
"Must be able to develop good system level understanding , analyze complex issues and translate into architecture and detailed specifications of IPs / sub-systems.
Must have very good understanding of Digital Design fundamentals and Front End Design Flow. Should have expertise in RTL design , synthesis, timing analysis, working with multiple clock domains. Should have good understanding of DFT aspects. Must have good verification and silicon validation knowledge . Knowledge of C++,System C or System Verilog is desired. Should have good documentation skills."
Requirements
Candidate must possess at least a Bachelor of Engineering/Technology or Master of Engineering/Technology in Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent.
Required skill(s): Digital IP/Subsystem Design.
Position : WIRELESS-DFT Engineers /Leads
Location Noida
Date Posted
Responsibilities
DFT for microprocessor core platforms and SOCs with tasks ranging from defining the SOC test architecture to DFT implementation and verification.
Hands-on experience with Test Encounter/Fastcan/DFT Advisor/Testkompress is a pre-requisite for the job.
2 to 7 years of experience for Engineer positions
7 years plus experience for Lead positions
Requirements
Candidate must possess at least a Bachelor of Engineering/Technology or Master of Engineering/Technology in Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent.
Required skill(s): DFT implementation and Verification.
At least 2 year(s) of working experience in the related field is required for this position.
Applicants must be willing to work in Noida.
Applicants should be Indian citizens or hold relevant residence status.
Preferably senior executives specializing in IT/Computer - Hardware or equivalent.
Full-Time positions available.
Position : Palladium
Location : Delhi (incl. Ghaziabad, Noida, Gurgaon & Faridabad)
Date Posted :
Responsibilities
Approx 5 years of experience.
Should have worked on: Netlist porting from RTL to Palladium.
Incorporation and verification of peripherals like SD Card , SIM Card , Memories etc.
Speed bridge creations.
Supporting Linux , tools team.
Verification using C, Verilog
Tool expertise on NC-Verilog , VCS , LEC.
Requirements
Candidate must possess at least a Bachelor of Computer Application , Bachelor of Engineering/Technology, Master of Computer Application/Computer Science or Master of Engineering/Technology in Computer Science/Information Technology, Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent.
At least 5 year(s) of working experience in the related field is required for this position.
Applicants should be Indian citizens or hold relevant residence status.
Preferably Senior Executives specializing in Engineering - Electronics/Communication or equivalent.
Full-Time positions available.
Position : WIRELESS-Physical Synthesis and Timing
Location Noida
Date Posted
Responsibilities
Would be responsible for physical synthesis and timing closure of Core platforms and SoC's. Responsible for generating chip level constraints, exceptions and achieving timing closure. Should be knowledgeable about floorplanning/routing/clock tree and DSM effects.
Should have an excellent hold on physical synthesis and optimization flow with hand-on experience in defining timing budgets, identifying exceptions, clocks balancing, delay & functional noise analysis & repair. Knowledge of design / RTL coding basics, commonly used clocking and low power schemes desired. Working knowledge of DFT aspects like Test insertion, scan chain tracing would be desired.
Experience with spice simulation tools and familiarity with floor planning , clock tree synthesis would be an added plus.
Requirements
Candidate must possess at least a Bachelor of Engineering/Technology or Master of Engineering/Technology in Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent.
Required skill(s): Spice simulation Tools, Floor planning.
PHY Design Engineer
Responsibilities:
Designing algorithms and architecture for next generation Wireless / Wired modem applications. Working with SoC design teams & S/W teams in realization of products.
"Must have strong experience in translating communication standards into Product Specifications. Should have knowledge of RF tracking loops, channel estimation, equalization, encoding , decoding, etc. Experience with floating and fixed point simulation is must in MATLAB / C++ / System C. Knowledge of WLAN, DVB, WCDMA, UMTS, WiMax, GSM/Edge, xDSL or other advanced digital wireless technology required. Must be willing to work on complete product life cycle from Definition to Silicon Validation. Knowledge of SoC Front End Design Flow and Lab Equipment is desired.
Must have excellent communication and documentation skills."
Requirements:
Candidate must possess at least a Bachelor of Engineering/Technology or Master of Engineering/Technology in Engineering (Computer/Telecommunication), Engineering (Electrical/Electronic) or equivalent.
Required skill(s): Wireless, Wired modem applications.
AMD
SoC Integration
B.Tech./M.Tech. in EE with 3-7 years work experience.
Work on RB45 implementation projects.
SoC Integration: Overlay, Bump planning, Floorplanning, chip build. Debug LVS/DRC errors.
Resource needed for enabling RB45 Implementation projects.
Design Implementation
B.Tech./M.Tech. in EE with 3-7 years work experience.
Work on GH45 implementation projects.
Design Implementation: logic design, timing-closure, electrical-closure, formal verification.
CAD
Experience :
- 5 to 7 years in CAD development and support, preferably around commercial synthesis and place and route tools. or equivalent experience implementing SaPR on a processor design.
Job Description :
- Participate in the development and support of synthesis and place & route CAD flows for high-performance low-power SOC and CPU's.
- Will work extensively with implementation team on developing a methodology for Synthesis and P&R style portion of design.
- Position requires extensive knowledge of at least one commercial SAPR EDA tool.
- Experience in CAD support of processor-based custom designs preferred .
- Strong software engineering and scripting skills is a must.
Education:
BS or MS CS/EE
Implementation
The requirement is primarily in hand implementation of x86 core modules.
- Understanding RTL verilog and interpreting the behavior
- Translating RTL into gate level schematic, manual place & route. Perform timing analysis, IR drop and design closure etc
- Meet clock rate, power and die size goals
- Verification of implementation against RTL using formal verification (LEC)
- Exposure to Synthesis, Autoplace & Route
- Gate level timing simulation
- Be able to perform different implementation tradeoffs
- Be able to communicate effectively with US counterparts and local team
- Microelectronics or VLSI education background is desirable and is a plus
- Exposure to Processor Architectures, pipelining, datapath is desirable
Senior MTS or MTS Microprocessor Design Engineer
Job Description
Work with the team that will advance high speed digital design technologies to the next generation. You will contribute to the development of advanced logic, circuits, techniques, and methodologies, culminating in the realization of next generation microprocessor products in deep submicron processes. Primary job responsibility is to lead a group of engineers to design high performance, reliable, implementation of complex processor micro architectures using deep sub-micron silicon processes. Job tasks include providing direction and overseeing high frequency logic and circuit design, collaborating with physical design, circuit, and process technology teams, to perform design trade off, and realize area, power and performance optimized silicon implementations.
Desired Profile
The candidate should have at least a bachelors or Masters or PhD degree (EE, EN,CE) with at least 3 years of VLSI design experience, preferably with exposure to custom high speed logic/layout development. The candidate should have prior experience in leading design teams. Ideally the candidate should have been through several microprocessor design cycles. In addition should have a sound u nderstanding of VLSI fundamentals encompassing devices, circuits, and logic families. Should have experience with performing timing/critical path analysis, and resolving speed path issues. Should have experience placing/routing standard cell functional blocks to achieve area/performance targets. Knowledge of low power circuits and power management techniques is highly desirable.
Should be familiar with block and chip level logic/functional verification, physical design/chip integration and circuit modeling/ simulation tools & techniques.
Should be adept in programming / scripting (C++, Perl, etc), and be conversant with flows and tools for VLSI chip development.
Knowledge of PC systems and Processor architectures/micro architectures in general, and AMD x86 architecture in particular, is a strong plus.
Senior MTS or MTS Microprocessor Verification Engineer
Job Description
Work with the team that will ensure the next generations of Microprocessors achieve their full potential. Your team will advance the state of the art of Microprocessor verification to the next level.
Primary job responsibility will be to lead a group of engineers to perform logic and functional verification at both the block and chip levels. You will provide guidance direction to the team and also communicate team's progress on a periodic basis to identify functional anomalies and debug to root cause. You will develop verification strategies, incorporating automated checkers, directed tests, and stress tests. You will develop, integrate, and use, tools and techniques for block and chip level functional verification and debug. You will contribute to the development of a comprehensive verification environment through the integration of several tools/flows.
Job responsibilities also include interacting with micro architects, design/implementation teams as well as product & test engineering teams to identify, resolve, and document design bugs/anomalies and contribute to the generation of silicon test /characterization suites.
Desired Profile
The candidate should have at least a bachelors degree (EE, EN,CE) with at least 4 years of VLSI functional verification experience, preferably with exposure to complex, high speed custom VLSI products . Candidates with a MS/PhD, emphasizing advanced chip/system verification, and with relevant practical experience can also apply. The candidate should have a sound understanding of logic/functional verification fundamentals encompassing functional test strategies, directed and stress test generation, verification infrastructures, and verification/debug flows. Should be adept in programming / scripting (C++, Perl, etc), and be conversant with flows and tools for VLSI logic/functional verification. Should be familiar with formal verification concepts and tools.
Knowledge of PC systems, Processor architectures/micro architectures, buses, and memory sub-systems in general, and AMD x86 architecture in particular, is highly desirable
Nokia
Position
Job Description
Skill Sets
Experience
PP-ASIC Solutions-Subsystem IP Sr Design Engineer, Power Specialisation- 08/07
Subsystem IP team is responsible for integration of various cellular wireless domain IP blocks together with multiple processors to create a complete cellular wireless subsystem.
This position requires experienced design engineers with focus on Low power design techniques used in nanometer process nodes (90nm, 65nms and lower)
B.E/BTECH/M.E/MTECH form reputed Worked on SoC and IP front-end power minimization techniques for low power designs
Good knowledge on low power design and advanced power management techniques.
VHDL/Verilog RTL coding.
Experience with Power estimation tools flows and techniques
Good knowledge of synthesis, static timing analysis and formal verification.
Experience with working on nanometer ASIC process nodes (90nm, 65nm or less) and knowledge of low power techniques in these process nodes.
5+ yrs
PP- Subsystem IP Senior Design Engineer, Synthesis,STA -08/07
This position requires experienced design engineers with focus on implementation and back-end. Main responsibilities include Logic Synthesis, Physical synthesis, Timing constraints development and Static timing analysis especially for nanometer technology nodes.
Strong Experience in DesignCompiler, PrimeTime, PrimeTime-SI, Blast RTL
Worked on ARM or processor based ASIC/IP design projects with Synthesis/Timing closure responsibilities
Experience in Constraint Development (functional and test modes) for multi million gate ASICs
Expertise in Tcl, Perl, Awk, Shell scripting
Understanding of VHDL/Verilog RTL coding for Synthesis and Timing
Exposure to the back-end tools (BlastFusion, Physical Compiler)
Experience in Formal Verification (Formality or LEC)
Experience with working on nanometer ASIC process nodes (90nm, 65nm or less)
5+yrs
Job Title: PROJECT LEAD - EXTRACTION
Other Information
BE/BTech or ME/MTech with 5+ years of experience in VLSI physical design or CAD methodology development. Experience in extraction preffered with some background on timing/crosstalk analysis, familiarity with spice. Experience with some of the following tools is preferred : Star-rcxt, Quickcap, Magma. Software skills should include Perl, TCL and shell scripts. Experience with Unix operating system is required. Should have indepth understanding of extraction concepts and solutions., awareness of vendor tools available, close exposure to one or more of available vendor tools, quality assurance
Supervision and talent management. Should be able to sense pulse of people and motivate them towards their personal/team goals, should be able to rally the team behind self towards achieving the team goals. Needs to have a strong customer focus. Will need to work closely with design teams at various geographical locations and across multiple business units. Will need good vendor management skills. Need to have strong communication skills. The candidate must have good critical analysis skills, should have an aptitude to learn and contribute. Leadership skills are a must. Prior experience in people management is preferred.
Responsibilities
Project Lead for Extraction domain which includes both transistor level and gate level extraction flows. To define, develop and deploy leadership extraction solution for 65 and 45 nm technology nodes. To deliver comprehensive solution covering aspects of quality assurance, cycletime and accuracy by modeling newer technology effects. Work closely with all stakeholders and customers to provide continuous support. Needs to work closely with SiTD to identify and model new systematic variations.
The flow is developed around vendor tools. This requires significant knowledge of vendor tools and methodologies to ensure comprehensive vendor tool qualification and benchmarking. Requires continuous interaction with vendors to drive the roadmap and solution in tune of TI's requirements.
Job Title: STA EXPERT
Skills and competencies required :
Experienced SoC backend design engineer
Design/Methodology Experience with Static Timing Analysis. Primetime-Primetime-SI
Timing closure, Signal Integrity, OCV, timing constraints development , timing libraries, Clock tree synthesis analyze
Knowledge of Perl and Tcl preferred
4-6 years experience
Good communication skills
Responsibilities
This job relates to a position within a team who is in charge of the development of the wireless ICs using the leading edge of the technology.
As part of a very dynamic engineering team, you will be responsible of developing, specifying and verifying System-On-Chip architectures for mobile phone devices. This mission consists of:
Implementation of high complexity digital basebands in 90 and 65 nm technologies, with low power techniques and usage of most up to date design flows
Gate and RTL level timing analysis
Work with teams designing high-speed ASICs
Identifying and developing a validation and verification framework for the DBB SOC architecture.
Job title: SOC hardware and validation Engineers
Presentation of the organization:
This job relates to a position within a team who is in charge of the development of the wireless ICs using the leading edge of the technology.
Description of the job:
You will be part of a dynamic design team with main responsibilities covering the ASIC design, integration, validation and test creation for a System-On-Chip targeted for the mobile phone digital based band modem implementing the GSM/GPRS/EDGE standards.
This SOC DBB design integration requires the execution of the following main activities:
Ø Wireless SOC hardware design
o RTL development
o Synthesis
o Validation
Ø Implement high quality validation methods:
o RTL coding and rules checking, RTL and gate simulation, formal equivalence, RTL & gate power aware simulation, code coverage, formal verification, post synthesis validation ...
Ø Specification of the validation and test suites development
o Developing test and DSP/MCU SW code ensuring the required coverage at the different abstraction levels
o Develop complex testbenches for both validation and test vector creation
Skills and competencies required/appreciated:
Ø ASIC/SOC design flow
Ø RTL coding
Ø Low level software development: DSP and MCU (C & ASM)
Ø Complex mixed C/HDL testbench development
Ø Validation tools/languages: Modelsim, VCS, Specman, UML,...
Ø Knowledge in GSM/GPRS/EDGE/UMTS technology is highly desirable
nVidia
Sr ASIC Designer (4 – 12 Yrs)
As a Senior ASIC Designer at NVIDIA design and implement the industry's leading Graphics, Video and Media & Communications Processors. Specific areas include 2D and 3D graphics, mpeg, video, audio, network protocols, high-speed IO interfaces and bus protocols, and memory subsystem design. In this position, you will be responsible for Architecture and micro-architecture design of the ASICs, RTL design and synthesis, Logic and Timing verification using leading edge CAD tools and Semiconductor process technologies. In addition to this, you will also mentor and guide more junior engineers. Requirements:5 to 10 years of complex high speed ASIC Design experience. Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, C++ programming languages, CMOS transistors and circuits is required. Previous design experiences in a project leadership role a plus. Previous experience mentoring junior engineers a plus Good communications skills and ability and desire to work as a team player are a must. BSEE, MSEE or PhD and CGPA of 8.0 out of 10.0 or higher is required.
Sr Physical Design Engineer (5 – 12 Yrs) Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets. Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure, - Static timing analysis, power and noise analysis and back-end verification across multiple projects. Requirements:BSEE or BSCS 7+ years of experience in large VLSI physical design implementation on 90, 80 or 65 nanometer technology. Successful track record of delivering products to production is a must. Understanding of custom Macro blocks such as RAMs, CAMs, high-speed IO drivers. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues. Working knowledge of deep sub-micron routing issues as they relate to power and timing. Circuit level comprehension of time critical paths. Spice experience a plus. Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma. Proficiency using Perl, TCL, Scheme, Make scripting is preferred
DFT Engineer (5 – 10 Yrs)
As a DFT engineer at NVIDIA, you?ll be responsible for designing key DFT logic modules, verifiying them. These include test mode controllers, IO bist, Memory Bist, Jtag In addition you will be responsible for scan insertion and ATPG.MINIMUM REQUIREMENTS:BSEE required, MSEE preferred.4 to 7 years of experience in DFT / design field.Strong logic Design and verification back ground with experience in STA. Must possess a strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.Programming in Perl, tcl and c++ is a plus
Looking forward to be of assistance to you or any of your friends who may be seeking a decent career change at this point of time, Pass it on.